Read "Streaming Systems" 1&2, Streaming 101 Read "F1, a distributed SQL database that scales" Read "Zanzibar, Google’s Consistent, Global Authorization System" Read "Spanner, Google's Globally-Distributed Database" Read "Designing Data-intensive applications" 12, The Future of Data Systems IOS development with Swift Read "Designing Data-intensive applications" 10&11, Batch and Stream Processing Read "Designing Data-intensive applications" 9, Consistency and Consensus Read "Designing Data-intensive applications" 8, Distributed System Troubles Read "Designing Data-intensive applications" 7, Transactions Read "Designing Data-intensive applications" 6, Partitioning Read "Designing Data-intensive applications" 5, Replication Read "Designing Data-intensive applications" 3&4, Storage, Retrieval, Encoding Read "Designing Data-intensive applications" 1&2, Foundation of Data Systems Three cases of binary search TAMU Operating System 2 Memory Management TAMU Operating System 1 Introduction Overview in cloud computing 2 TAMU Operating System 7 Virtualization TAMU Operating System 6 File System TAMU Operating System 5 I/O and Disk Management TAMU Operating System 4 Synchronization TAMU Operating System 3 Concurrency and Threading TAMU Computer Networks 5 Data Link Layer TAMU Computer Networks 4 Network Layer TAMU Computer Networks 3 Transport Layer TAMU Computer Networks 2 Application Layer TAMU Computer Networks 1 Introduction Overview in distributed systems and cloud computing 1 A well-optimized Union-Find implementation, in Java A heap implementation supporting deletion TAMU Advanced Algorithms 3, Maximum Bandwidth Path (Dijkstra, MST, Linear) TAMU Advanced Algorithms 2, B+ tree and Segment Intersection TAMU Advanced Algorithms 1, BST, 2-3 Tree and Heap TAMU AI, Searching problems Factorization Machine and Field-aware Factorization Machine for CTR prediction TAMU Neural Network 10 Information-Theoretic Models TAMU Neural Network 9 Principal Component Analysis TAMU Neural Network 8 Neurodynamics TAMU Neural Network 7 Self-Organizing Maps TAMU Neural Network 6 Deep Learning Overview TAMU Neural Network 5 Radial-Basis Function Networks TAMU Neural Network 4 Multi-Layer Perceptrons TAMU Neural Network 3 Single-Layer Perceptrons Princeton Algorithms P1W6 Hash Tables & Symbol Table Applications Stanford ML 11 Application Example Photo OCR Stanford ML 10 Large Scale Machine Learning Stanford ML 9 Anomaly Detection and Recommender Systems Stanford ML 8 Clustering & Principal Component Analysis Princeton Algorithms P1W5 Balanced Search Trees TAMU Neural Network 2 Learning Processes TAMU Neural Network 1 Introduction Stanford ML 7 Support Vector Machine Stanford ML 6 Evaluate Algorithms Princeton Algorithms P1W4 Priority Queues and Symbol Tables Stanford ML 5 Neural Networks Learning Princeton Algorithms P1W3 Mergesort and Quicksort Stanford ML 4 Neural Networks Basics Princeton Algorithms P1W2 Stack and Queue, Basic Sorts Stanford ML 3 Classification Problems Stanford ML 2 Multivariate Regression and Normal Equation Princeton Algorithms P1W1 Union and Find Stanford ML 1 Introduction and Parameter Learning

TAMU Operating System 1 Introduction


Support from OS

  1. Support for Asynchronous Events
    • example
      • events from devices
      • user input
      • timer events
    • methods
      • Polling
      • Interrupt-driven
  2. Hardware Protection
    • user mode vs. supervisor mode
    • privileged instructions
      • all I/Os
  3. Support for Address Spaces
  4. Timers
    • Timers can be set, and a interrupt occurs when the timer expires.


When an interrupt occurs, the CPU:

  1. stops
  2. saves state
  3. changes into supervisor mode
  4. branches to predefined location.

Return-from-interrupt (rti) automatically restores state. Interrupts/Exceptions can be invoked by asynchronous events (I/O devices, timers, various errors) or can be software-generated (system calls).

System calls

Example in 32-bit Linux:

  1. load system call number in register eax
  2. load arguments to system call in registers
    ebx , exc , edx , esi , edi , ebp
  3. invoke software interrupt: int 0x80
  4. Returned values are stored in eax

Software interrupts are expensive! Compiler optimization not possible.

  • Cost of context switch (saving/restoring registers)
  • Caches are stale
  • TLBs
  • CPU pipelines

Why still interrupts or system call?

  • Can load user program into memory without knowing exact address of system functions.
  • Separation of address space, including stacks: user stack and kernel stack.
  • Automatic change to supervisor mode.
  • Can control access to kernel by masking interrupts.

Handling exceptions on x86

Interrupt descriptor table (IDT)

  • Interrupt Vector Table x86-style:
    • processor exceptions, hardware interrupts, software interrupts
  • 256 entries: Each entry contains address of interrupt handler (interrupt service routine).
  • The first 32 entries reserved for processor exceptions (division by zero, page fault, etc.)
  • Hardware interrupts can be mapped to any of the other entries using the Programmable Interrupt Controller (e.g. 8259 PIC)

The exception handling procedure is as below.

Exception 1

There are 4 steps here,

  1. save states
  2. call dispatch function
  3. load states
  4. return from interrupt

Exception 2


This is my class notes while taking CSCE 611 at TAMU. Credit to the instructor Dr. Bettati.

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